1. Technical Field
A DC analog circuit is disclosed which monitors a dynamic random access memory (DRAM) sample cell access device, and outputs a DC reference voltage to a word line voltage regulation system. The resulting output voltage, Vpp, from the word line voltage regulation system, will then vary in accordance with the cell access device parametrics to guarantee that a full high-level voltage will always be written into the DRAM cell.
2. Related Art
A typical DRAM must operate within the framework of the overall system timing and global bus scheduling. Therefore, the DRAM architecture as well as individual memory cell designs are closely tied to timing issues.
The global bus serves as both the address bus and the data bus. One consequence of this arrangement is that a read or write operation to the DRAM memory core takes exactly two system clock cycles. In the first, or address, cycle, the read/write memory address is presented on the global bus and is latched in by the address register on the DRAM chip. In the second, or data, cycle, the DRAM receives the write enable control bit and the write data (if any). During this second cycle, data is either written to, or read from, the memory core and subsequently presented on the global bus.
A refresh cycle, however, operates somewhat differently. During a refresh cycle, an internally generated row address selects a row in the memory to be refreshed. In column-wise parallel fashion, the (inverted) row data is read out, inverted by the refresh circuitry, and then written back into the same row. To ensure device reliability, the voltage level of this write back signal must be both of a sufficient amplitude and free of ripple or other induced noise. The column and row addresses may be either loaded separately, on sequential clock cycles, or they may be presented at the same time.
One problem faced by DRAM designers is to select a sample cell access device circuit 100 having a word line WL voltage, Vpp, (FIGS. 1A, 1B) that is adequately high to achieve a full writeback level in the cell when the cell access device is weak (i.e., there are a high threshold voltage (Vt), a long channel, a narrow width, and a thicker oxide), while at the same time not exceeding the breakdown voltage of the dielectric material in the cell structure. One common solution is to fix the word line voltage Vpp as high as possible near the reliability limits of the technology. In process cases where the cell access device is weak, this fixed voltage solution is inadequate. The cell writeback signal will fall short of its bitline xe2x80x9chighxe2x80x9d voltage (VBLH) goal, as illustrated in FIG. 1B by voltage curve 150.
An improvement sought by many designers involves monitoring a sample cell access device and automatically adjusting the word line voltage, Vpp, to a level which tracks the threshold fluctuations of the cell device, at a minimum, to insure that it is always conductive when the source is at bitline potential. Curve 160 in FIG. 1B illustrates this concept. The advantages of such an improved method would be a lower nominal word line voltage giving rise to better reliability and lower current consumption from the word line voltage regulation system.
Another approach that has been attempted in the related art is illustrated in FIG. 2. A diode-connected sample cell access device 280 is installed in the feedback path 270 of the Vpp word line voltage system monitor 250, as shown in FIG. 2. This approach, however, has several disadvantages. First, the drain and source voltages of the sample cell access device 280 do not correspond to the actual operating drain and source voltages of the cell device 280 near the end of writeback of a xe2x80x9chighxe2x80x9d level. Also, the resistive divider formed by resistors 240 and 260 attenuates the sample cell access device 280 process fluctuations, thereby reducing compensation effectiveness. Yet another disadvantage arises because the sample cell access device 280 must operate at low microampere (e.g., approximately 1 to 5 xcexcA) current levels in order to mimic the actual cell charging current. Microampere currents transform into an impedance level, of the combined device and resistive divider 240, 260, in the several hundred thousand ohms range. This high impedance, combined with unavoidable stray capacitance, slows the response time of the feedback loop 270, in turn causing excessive overshoot of the Vpp goal voltage before the charge pump 220 shuts off. This effect produces an unacceptably high ripple voltage on Vpp.
An improved prior art method taught by Foss et al. (U.S. Pat. No. 5,267,201, incorporated herein by reference) utilizes the sample cell access NFET device 350 in the feedback loop in a different manner, as shown in FIG. 3. PFET devices 360 and 370 comprise a current mirror connected between Vpp and the drain of sample cell access device 350 to sense its current. The current mirror drives the drain of NFET device 380 operating in the linear region as a resistive load and outputs a voltage to drive the inverters 410 and 420 to produce a logic level inhibit signal for switching the oscillator 440 on and off. The Foss circuit realizes two advantages over the approach embodied by the circuit of FIG. 2. First, the source of NFET device 350 is properly referenced to the bitline high voltage Vdd (same as VBLH) as desired, and secondly, Vpp must achieve a high enough voltage for current to flow in NFET device 350 before an inhibit signal can be generated.
Although Foss has taught improvements, the circuit (FIG. 3) still suffers drawbacks. One drawback is the sample device current variation with the drain voltage set by diode-connected PFET 360 which has its own parametric fluctuations unrelated to the memory cell device. Sensitivity to this effect will be significantly magnified in very short channel (i.e. approximately 0.15 microns) modern DRAM technologies compared to the technology of the Foss era. Also, current through NFET device 350 that triggers an inhibit signal compares to the strength of the linear region NFET device 380. Again, parametric variations of NFET device 380 will also influence the Vpp level unrelated to the cell device.
Increasing load current demand on the Vpp regulation system of modern day synchronous DRAMs (SDRAMs) presents a tougher design challenge especially if decoupling capacitance is limited. Stronger charge pumps combined with limited decoupling capacitance require faster transient response from the Vpp level monitor to suppress Vpp ripple. Foss""s approach still relies on a sample cell access device located in the feedback loop contrary to the fast transient response requirement.
The present invention discloses a circuit and method which overcome all of the related art disadvantages, while at the same time achieving more precise control of Vpp and guaranteeing a full cell writeback level. This circuit overcomes the major loop response problem of the related art by avoidance of the sample memory cell access device in the feedback loop of the Vpp regulation system. Instead the sample cell access device is operated in a circuit under steady state DC conditions and outputs a DC reference voltage that changes in accordance with the parametrics of the sample memory cell access transistor. This DC reference voltage then becomes the reference supplied to the Vpp level monitor in the Vpp voltage regulation system.
The present invention provides a method of biasing and monitoring a sample cell access device for regulating the word line selection voltage of a dynamic random access memory (DRAM) chip, said method comprising: providing a sample cell access device wherein said sample cell access device substantially tracks the process parametric fluctuations of any one of a plurality of memory cell access devices within the DRAM chip; forcing a constant DC current through said sample cell access device; providing a DC voltage equal to the bitline selected voltage applied to a first terminal of said sample cell access device; and providing an amplifying circuit connected between the gate terminal and a second terminal of said sample cell access device for regulating the voltage at the second terminal of said sample access device at a predetermined voltage less than the bitline selected voltage wherein said amplifying circuit outputs a reference voltage.
The present invention also provides a word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM) cell, said word line voltage control circuit comprising: a sample cell access device; a circuit for forcing a fixed current through said sample cell access device; an amplifier circuit connected to the output of said sample cell access device; a feedback loop between said amplifier circuit and an input of said sample cell access device; and an output from said amplifier circuit to said word line of a dynamic random access memory (DRAM) cell.
The present invention further provides a method of employing a word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM), said method comprising: providing a word line voltage control circuit; providing a sample cell access device; forcing a fixed current through said sample cell access device; providing an amplifier circuit connected to the output of said sample cell access device; providing a feedback loop between said amplifier circuit and an input of said sample cell access device; and providing an output from said amplifier circuit to said word line of a dynamic random access memory (DRAM) cell.
The present invention additionally provides a word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM) cell, said word line voltage control circuit comprising: a sample cell access device; a circuit for forcing a fixed current through said sample cell access device; an inverting amplifier connected to the output of said sample cell access device; a level monitor connected to the output of said inverting amplifier; a charge pump connected to the output of said level monitor; a feedback loop between said charge pump and an input of said sample cell access device; and an output from said feedback loop to said word line of a dynamic random access memory (DRAM) cell.
The present invention further provides a method of employing a word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM), said method comprising: providing a word line voltage control circuit; providing a sample cell access device; forcing a fixed current through said sample cell access device; providing an inverting amplifier connected to the output of said sample cell access device; providing a level monitor connected to the output of said inverting amplifier; providing a charge pump connected to the output of said level monitor; providing a feedback loop between said charge pump and an input of said level monitor; and providing an output from said feedback loop to said word line of a dynamic random access memory (DRAM) cell.
The present invention still further provides a dynamic random access memory (DRAM) word line supply comprising: a voltage supply Vpp increasing from a voltage level insufficient to enable a memory cell access transistor for the word line toward a voltage level sufficient to enable said access transistor, for connection to the word line from time to time; the memory cell access transistor for connecting a memory cell capacitor to a bitline, having a gate connected to the word line; a sample transistor similar to the memory cell access transistor; a circuit for applying the increasing voltage supply to the sample transistor for causing the sample transistor to conduct, under voltage supply conditions similar to those required by the memory cell access transistor; a circuit for prohibiting increase of the voltage supply upon turn-on of the sample transistor; whereby the voltage supply having the voltage level sufficient to turn-on the memory cell access transistor is provided for connection to the word line.
The present invention also provides a semiconductor structure including a word line voltage control circuit for monitoring and regulating a voltage signal to a word line of a dynamic random access memory (DRAM) cell, said semiconductor structure comprising: a substrate; at least one access transistor on said substrate; at least one buried node electrically coupled to said access transistor; at least one monitor transistor electrically coupled to said buried node; and an access transistor bitline connection electrically coupled to said buried node.
The present invention provides a word line voltage control circuit for monitoring and regulating a voltage signal to a word line of a dynamic random access memory (DRAM) cell, said word line voltage control circuit comprising: a compensated reference voltage system; and a word line voltage regulation system.
The present invention additionally provides a word line voltage control circuit for monitoring a sample cell access device and regulating a word line voltage selection level of a dynamic random access memory (DRAM) cell, said word line voltage control circuit comprising: a sample cell access device; a comparator circuit for comparing a reference voltage output of the sample cell access device with a fixed reference voltage; at least one charge pump connected to the output of said sample cell access device, said at least one charge pump receiving an input from said comparator circuit; a feedback loop between said charge pump and an input of said sample cell access device; and an output from said feedback loop to said word line of a dynamic random access memory (DRAM) cell.